Technical Field
Embodiments described herein relate to data processing devices and more particularly, to implementing interconnect protocol configuration registers in memory.
Description of the Related Art
Computer systems are incorporating more complex memory devices, as well as large numbers and diverse types of memory devices, to cope with ever increasing data storage and performance requirements. One type of computer system may include a hybrid memory cube (HMC) of stacked memory dies, while other types of computer systems using other types of memory devices are also contemplated. Various types of memory devices may be utilized in these computer systems, including random-access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), high-speed complementary metal-oxide semiconductor (CMOS), high-density DRAM, embedded DRAM (eDRAM), 3D stacked memory (e.g., stacked DRAM), interposer-based integrated memory, multi-chip modules (MCM), off-chip DRAM on a motherboard, non-volatile RAM (NVRAM), magneto-optical storage medium, read only memory (ROM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), phase-change memory, spin-transfer torque magnetic RAM, memristor, extended data output (EDO) RAM, Rambus RAM, Rambus DRAM, erasable programmable memory (EEPROM), solid-state memory, hard disk drive, optical storage mediums, etc.
Computer systems often utilize one or more interconnects to enable communication between system components, such as between processors and memory. Interconnects can also be used to support connections to input/output (I/O) devices. Various types of interconnect protocols are currently in use today to support data transfer over different types of interconnects, and new interconnect protocols are continuously being developed and introduced into the marketplace. Interconnect protocols typically require some amount of dedicated register space for use as configuration registers. These configuration registers may be used by the physical/transport layer to set and store base address, capability, status, and other settings. Accordingly, interconnect protocols typically utilize extra physical hardware (e.g., static random-access memory (SRAM)) on interconnected nodes.
Various interconnects (e.g., Peripheral Component Interconnect Express (PCIe), HyperTransport™ (HT), RapidIO, etc.) can require at least a 4 kilobyte (kB) SRAM memory region for command and configuration registers. Moreover, heterogeneous system architecture (HSA)-compliant systems need to provide a table of HSA agent capabilities, which may be large. Implementing a dedicated register space for interconnect protocol configuration registers reduces the amount of space on the logic die that can be utilized for the processor or memory regions.